Technical Field
The present disclosure relates to electronic circuits. Particularly, the present disclosure relates to the design and implementation of integrated circuits. More particularly, the present disclosure relates to designing clock gating circuits.
Description of the Related Art
With the recent advancements in design and implementation of integrated electronic circuits, the emphasis has also been upon designing electronic circuits which bring about a reduction in power consumption and an increase in the overall efficiency of the semiconductor device which made operation using the said integrated circuit. One of the methods to bring about a reduction in the power consumption levels of a semiconductor device is to shut off the active clock inputs to the sequential blocks (circuits) thereof when (those sections/circuits are) not in use.
Sequential circuits typically have been the major contributors for power dissipation in the digital system since one of the inputs to sequential circuits is a clock which is switched on all the time. Further, since clock signal are heavily loaded most of the times and this phenomenon brings about an increase in the power dissipation. Further, to distribute the clock and to control the skew network, a clock network (also referred to as clock tree) incorporating clock buffers is constructed. The construction of clock tree with clock buffers makes a direct contribution to the increase in power consumption across the sequential circuits.
Clock gating is one of the conventional methods utilized to control and optimize the (electrical) power dissipated by a clock network and the corresponding sequential circuits, since in a typical semiconductor device, the clock network contributes significantly for power dissipation. One of the well known conventional techniques for saving electrical power in clock trees was to stop the clock fed into any idle modules thereof. The phenomenon of clock gating controls the switching of the clock network by selectively disabling the clock, whenever there has been no change in the state of a clock register.
Yet another conventional attempt towards reducing the power dissipation of sequential circuits involved using a pre-computation technique to generate a signal that controls the load enable pin of the flip flops in the data path. The control signal is typically derived by investigating the combinational blocks in the data path. However, the aforementioned technique is useful only if the outputs of the block can be pre computed (predicted) for certain input assignments.
Yet another conventional attempt towards reducing the power dissipation of sequential circuits involved the use of a latch based clock gating circuit in control-dominated designs. However, the drawback associated with this approach is that the additional latch based clock gating circuit when placed early in the clock tree to save clock tree power, has diminished timing budget for its setup time requirement. In order to improve the timing budget, plurality of latches are put later in the clock tree (near the sequential elements which receives gated clock). This approach defeats the purpose of saving the clock tree power, additional power is dissipated by plurality of lathes itself. In view of the foregoing, there was felt a need for an efficient and effective mechanism for gating the active clock edges and for ensuring improved power management and utilization in sequential circuits.